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choosebcd
- 基于vhdl的BCD码转ASCII码的设计，已经经过调试，可直接使用-Vhdl code based on the BCD to ASCII code of the design, debugging has been directly used
bcd_updown_counter2
- It is a simple 4-digit bcd up down counter written in verilog
seven_seg_decoder
- ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment
binary_to_bcd
- this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corres
digital-frequency
- 数字频率计 采用Verilog语言编写，分为8个模块，分别是计数器，门控，分频，寄存器，多路选择，动态位选择，BCD译码模块-Digital frequency meter using Verilog language, divided into eight modules, namely, the counter, gated, frequency, register, multiplexer, Dynamic Choice, BCD decoding module
bai2
- excercises verilog add two bcd numbers
a_bcd_counter_using_verilog
- 3 bits bcd counter using verilog
bcd_to_binary
- bcd to binary verilog
BCD
- 模为 60 的 BCD码加法计数器，采用verilog语言编写。-BCD code module for the addition of 60 counters, using verilog language.
verilog
- Verilog初学者例程:1位全加器行为级设计、1位全加器门级设计、4位超前进位加法器、8位bcd十进制加法器、8位逐次进位加法器、16位超前进位加法器、16位级联加法器、多路四选一门级设计、七段译码器门级设计-Verilog routines for beginners: a behavioral-level design full adder, a full adder gate-level design, 4-ahead adder, decimal 8-bit bcd adder, 8-
BCD-autoplus
- 利用Verilog HDL语言，编写一个2为BCD码加法器程序，并在DE2板是实现功能的运用。-Auto plus
bcd-decimal
- bcd to decimal verilog code
BCD
- Verilog hdl编写的二进制转BCD码程序-BCD binary switch program written in Verilog hdl
BCD
- 利用Verilog HDL语言实现BCD码的加法-Using Verilog HDL language implementation of BCD addition
BCD_ok-BCD
- Verilog 4位计时器,可以在CPLD开发板上成功运行-Verilog CPLD FPGA
binary_to_BCD
- 本人编写的2进制转换为BCD码的verilog程序，绝对可用，已测试通过。-I write binary to BCD verilog program, absolutely free, have been tested.
MATLAB-and-Verilog-codes
- there are 5 files. the first two codes are written in Matlab as m-files in control system design to show step responses. in contrast, the final three codes are written in verilog ( Quartus II) used in Altera one of them for BCD adder and the other fo
BCDma-verilog
- 二进制转bcd码，很好理解，适合新手用，可以学习学习-Bcd binary switch code, well understood, suitable for novice
Binary-BCD-code
- 用Verilog语言写的二进制转BCD码,可以作为课堂教学实验或者课后作业，有完整工程代码-Written in Verilog language transfer binary BCD code, can be used as a teaching experiment or the homework, a complete project code
BCD-Counter
- Verilog Module for parity